RISC-V: Open ISA, Processors and Hardware-Accelerated PULP Systems

Francesco Conti (University of Bologna, Italy)

Period:

Monday, June 9, 2025 to Friday, June 13, 2025

Year:

2025

Credits:

3.00

Duration:

Objectives

The course provides an introductory overview on the RISC-V instruction set architecture and on the PULP Platform project, which develops open-source, energy efficient computing architecture based on RISC-V, ranging from IoT microcontrollers to AI accelerators to HPC.

Program

Introduction to RISC-V ISA
Open-source RISC-V processors (CV32, Ibex, CVA6)
PULP Platform concepts
Customizing PULP processors
Hardware acceleration in PULP platforms

A minimum of 75% attendance is required.

Teaching methods

Frontal lectures + Hands-on laboratory sessions

Assessment methods

Final test (True/False + multiple-choice)

Bibliography

Preliminary knowledge expected is good understanding of computer architecture and C programming. Reference book:
- D. Patterson, J. Hennessy, Computer Organization and Design: the Hardware/Software Interface (RISC-V edition)

Previous knowledge of HDLs is appreciated, but is not required.

Schedule:

9 June 2025, 10:30AM – 12:30PM; 2:30 – 4:30PM
10 June 2025, 10:30AM – 12:30PM, 2:30 – 4:30PM
11 June 2025, 10:30AM – 12:30PM, 2:30 – 4:30PM
12 June 2025, 10:30AM – 12:30PM, 2:30 – 4:30PM
13 June 2025, 10:30AM – 12:30PM, 2:30 – 4:30PM

All lectures are held in room Garda (Pov01, second floor).

Menù

RISC-V: Open ISA, Processors and Hardware-Accelerated PULP Systems

Teaching methods

Assessment methods

Bibliography